View source for Meetings/Assignments -- CSC400-Circuit Design F2011

[[CSC400-Circuit Design on FPGA chips using VHDL | Main Page]] | [[Labs -- CSC400-Circuit Design F2011 | Lab Page]]
<br />
__TOC__
<br />

=9/13/11=
* Mini assignment --[[User:Thiebaut|Thiebaut]] 09:12, 13 September 2011 (EDT)
** Update the main wiki page for this IS and define what an FPGA is (1 paragraph), what VHDL refers to (1 paragraph), and what this IS is about; i.e. what your goals are, which is just a summary of what we discussed at our first meeting.
** Since this is a wiki, you'll have many opportunities to refine these 3 paragraphs as the semester goes on, so don't worry too much about making it super accurate.


=9/14/11=
* Good first official meeting.  Demo of a counter circuit downloaded into the Cool-Runner board.  Circuit updates 7-segment displays.

<center>
[[Image:coolrunner91411.jpg|600px]]
</center>
* Assignment for next meeting:
** Keep playing with the software and Cool-Runner chip
** See if schematics of counter circuit can be modified/edited.   If possible, make a change, compile the schematics, download, and see if behavior changes.   Some ideas of possible modifications:
*** make counter count twice as fast, or 10 times as fast
*** make counter display 0000 and stop
*** make counter stop when it reaches a special value, i.e. when binary pattern kept internally in flip-flops reaches a value s.a. 1000 and the leading 1 resets the counter, or something similar.
** Keep track of process required to modify the circuit.  Make it a short lab, if possible (don't worry about format or completeness at this point), and add it to the Labs page.


=9/26/11=
--[[User:Thiebaut|Thiebaut]] 14:34, 26 September 2011 (EDT)

Just wanted to share what I have discovered when going through the tutorial at http://www.xilinx.com/itp/xilinx7/books/docs/qst/qst.pdf

On Page 11, when defining the family, instead of Spartan 3, use Coolrunner II.  Also instead of xc3s200, I used xc2c256 as the device (which is what I read on the chip on the kit).

On Page 16, for target device I used xc2c256.

On Page 17: I simply copied and pasted the code in Verilog in the edit window.

On Page 19: I used the constraint editor to define the length of time the clock was high to 20ns, and set its duty cycle to 50%.   Note that this tutorial was written for ISE Version 7 and we have Version 11, which is quite different... :-(

On Page 20: I found out that the waveform editor no longer exist in ISE.  So to generate a waveform for what the DIRECTION signal should be, it will have to be done manually rather then modifying a diagram, as indicated on the page.
The main trick when trying to follow the tutorial is to figure out which window to look in, and how to get some windows to show up.  For example, in the "Design" tab (lower left), at the top of the "Design" page, you have a "Sources for:" bar with 3 options: Implementation, Behavioral Simulation, and Post-Fit Simulation.   It took me a while to figure out that they opened up different kinds of options...


=10/5/11=
*Walked through a portion of the In-depth Tutorial for the Xilinx ISE Design Suite 11. The tutorial was much more complex than what we need to make the labs, and much of the functionality were not applicable to the CoolRunner-II hardware.

*Assignment for next meeting:
**Try to create a project that has the complexity of the Quick Start Tutorial from Xilinx, using the In-depth Tutorial as a guide.

*'''UPDATE''' Found a much better tutorial from the Digilent, Inc. website for programming the CoolRunner-II in Verilog as well as using Schematics: [http://www.digilentinc.com/Support/Support.cfm?ProdCat=&DocType=Tutorials Digilent Tutorials]--[[User:Tliu|Tliu]] 13:53, 11 October 2011 (EDT)


=10/12/11=
--[[User:Thiebaut|Thiebaut]] 12:27, 12 October 2011 (EDT)
* Great meeting today!  We (Tiffany) broke the information-complexity wall! 
* Tiffany found a nice repository of tutorials by Digilent.  Surprisingly these do not show up in Google searches, otherwise we'd have found them earlier
* Tiffany demonstrated the running of a simple 4-input logic circuit in the CoolRunner board.  No clocks yet!

;Assignment for next week (and possibly weeks to come)
* Create one or two mini-labs based on Digilent's first 2 tutorials: one with Verilog input, one with schematics input.
** Explain steps necessary to get the Webstart licence from Xilinx to use their software system
** Add reference to digilent's tutorial and cache it on this wiki
** Add zip archive-file with the different files created
** Add photos of kit with output LED activated
** Show edits necessary to change output from one LED to another.
* Add a new page with information about pins and LED names that can be used from within a circuit.
* Questions in need of exploration or just some thinking...
** How can we energize the inputs programmatically, i.e. use a simulator to generate the truth table of the circuit?
** How could we swap software for hardware, i.e. take the core of a very busy loop in a program and port the computation to an FPGA?
* Start thinking of taking the CSC270 labs and porting them to the CoolRunner II.   Purely sequencial circuits should be fine for right now.   Figure out how to create a decoder module, and how to use one already wired.  Same for multiplexer.   Start about creating a page with several modules.

=10/19/11=
--[[User:Thiebaut|Thiebaut]] 08:16, 20 October 2011 (EDT)
* We now have two mini-labs for creating a circuit using
** Verilog as the input 
** Schematics
:and Tiffany illustrated both.
* We explored the different options available for designing a circuit schematics:
** decoders
** multiplexers
** counters
** flip flops
** simple logic of and, or, inverters (we didn't check for nands and nors, but they should logically be there)
** TTL (some standard circuits, s.a. counters are available given their 74XXX part number)

==Assignment for next Week==
* Look up if there is a debouncing template available for "debouncing" the signal generated by input switches.  It is not important for pur logic circuit, but will be for sequencial circuit.
* Implement a simple frequency divider with a counter, using its MSB output as the divide-by-16 version of the clock.  See how you could generate a 1Hz (or close to 1Hz) clock signal from the slowest clock available on the board.
[[Image:7SegmentCode.gif|right|150px]]
* Figure out a way to activate all 8 LEDs of a 7-segment display (the decimal point is the 8th one!) using some kind of counter + decoder circuit.   Note: you need to find a circuit that takes as input one signal and that, depending on this signal's polarity, turns one of the 7-segment's LEDs ON or OFF.
* Figure out how to simulate the logic of a circuit without having to download it into the FPGA.   We should be able to generate a truth table for the circuit via simulation.
<br />
* '''If you have time''', start creating FPGA versions of the CSC270 labs.  I'm listing below all the labs that we should try to do this semester.   Start at your own pace... :-)
** [http://cs.smith.edu/dftwiki/index.php/CSC270_Lab_2 Lab 2], with its 2-bit and 3-bit adder.  Skip the transistor part.  For each one, use Verilog, and schematics input.
** [http://cs.smith.edu/dftwiki/index.php/CSC270_Lab_3_2011 Lab 3].  Just show how to create a 3-to-8 decoder with the FPGA and connect its output of a 7-segment display.
** Lab 4: skip
** Lab 5: skip 
** [http://cs.smith.edu/dftwiki/index.php/CSC270_Lab_6_2011 Lab 6]: Do Machines 1 and 2, in Verilog and with schematics.
** [http://cs.smith.edu/dftwiki/index.php/CSC270_Lab_7_2011 Lab 7]: Yes!  the GYR sequencer.  
** We'll have to come up with some project/lab where we implement the same logic (say a GYR sequencer) with all three platforms available (discrete logic on the digital kit, microprocessor with the 6800, and FPGA) and compare which can run the fastest...
<br />
=10/26/11=
* "Stuck" is the keyword for the day...
* We are going to go one step at a time and implement these simple designs
*# Get external clock signal and feed it to one output pin.  Connect the scope to it, and see the signal.  Take a picture.  Figure out the frequency and duty cycle.
*# Once that works, add a divide-by-16 4-bit counter to the design.  Both clock and MSB should go to output pins.  Use the scope to capture the clock and the MSB.  verify that one is 16 times slower than the other one.
*# Once that works, put 3 or 4 divide-by-16 in series and see how close to 1 Hz we can get...
*# Figure out how to simulate a circuit with a Verilog test module.

<br />

<br />

<br />

<br />

<br />

<br />
[[Category:CSC400]][[Category:VHDL]][[Category:FPGA]]